1. Technical Field
The present invention is directed to the field of phase locked loops. More specifically, the invention provides an improved phase locked loop ("PLL") that includes an analog holdover mechanism. The analog holdover mechanism enables the PLL to continue to operate without a large frequency shift when there is a problem with the external reference clock signal.
2. Description of the Related Art
Phase locked loops are well-known elements in analog and digital circuit design. A phase locked loop operates by receiving an external reference clock signal and generating a localized oscillator signal that is synchronized with the external reference clock signal. The local oscillator signal may operate at the same frequency as the reference clock signal or at some integer multiple of that frequency. A general description of the theory and operational characteristics of a PLL is contained in Couch, Digital and Analog Communication Systems, Fourth Edition, pp. 289-296.
FIG. 1 is a circuit diagram of a known PLL circuit 10. This circuit 10 includes four primary elements--a phase detector 14, an operational amplifier 26, a voltage controlled oscillator (VCXO) 32, and a counter 36. This circuit 10 generates a local oscillator signal (PLL clock) 34 that is synchronized with an external reference clock signal 12, but which operates at a higher frequency than the external reference clock 12. This is accomplished by feeding back a divided down version 38 of the local oscillator signal 34 to the phase detector 14, which then compares the phases of the reference clock signal 12 with the feedback signal 38.
The phase detector 14 has two inputs and two outputs, The two inputs of the phase detector 14 are coupled to the external reference clock signal 12 and the PLL feedback signal 38, and the two outputs 16A, 16B are coupled to the operational amplifier 26. If the PLL feedback signal 38 leads in phase with respect to the reference clock signal 12, then the phase detector 14 outputs a pulse on the negative phase output (ph-) 16A. Similarly, if the reference clock signal 12 leads in phase with respect to the PLL feedback signal 38, then the phase detector 14 outputs a pulse on the positive phase output (ph+) 16B. These output pulses on the positive and negative phase outputs 16A, 16B from the phase detector 14 are characterized by a pulse width that is equivalent to the phase difference between the two inputs.
When the phase difference between the reference clock signal 12 and the PLL feedback signal 38 is nearly zero degrees (i.e., when the PLL is "locked"), then the phase detector enters an operational region in which it cannot discriminate the phase difference between the two input signals. This operational region is referred to herein as the "mdead zone." As the phase difference of the two inputs approaches zero degrees, the phase detector 14 outputs minimum-width pulses on both the positive and negative phase outputs 16A, 16B.
The phase detector outputs 16A, 16B are coupled to the operational amplifier 26 through a pair of RC circuits. These RC circuits configure the operational amplifier 26 as an integrator 40. The negative phase output (ph-) 16A is coupled to the negative input of the operational amplifier 26 through the RC circuit composed of resistors 18, 28 and capacitor 30. And the positive phase output (ph+) 16B is coupled to the positive input of the operational amplifier 26 through the RC circuit composed of resistors 20, 22 and capacitor 24.
This integrator 40 receives the pulses from the phase detector outputs (ph+, ph-) 16A, 16B and generates a voltage level at its output that is proportional to the pulse width of the phase pulses. This phase voltage is then provided as an input to the voltage controlled oscillator (VCXO) 32.
The voltage controlled oscillator 32 generates an output clock signal, PLL clock 34, which is characterized by a frequency that is proportional to the phase voltage from the integrator. This clock signal, PLL clock 34, is the localized oscillator signal that is synchronized with the external reference clock 12. The PLL clock signal 34 is then fed back to one of the inputs of the phase detector 14 either directly, or via a counter 36.
The counter 36 is configured as a divide-by-N counter, and it generates the PLL feedback signal 38, which is a frequency divided version of the PLL clock signal 34. By selecting an appropriate value of N. a circuit designer can select the frequency of the PLL clock signal 34 with respect to the external reference clock 12. For example, if the circuit designer desires to generate a synchronized version of the reference clock signal 12, but at a frequency 10 times greater than the reference clock signal 12, then the value of N would be 10.
FIG. 2 is a timing diagram showing the operation of the PLL set forth in FIG. 1. This timing diagram sets forth, from top to bottom, the PLL clock signal 34, the reference clock signal 12, the PLL feedback signal 38, and the corresponding phase pulse signals on the positive and negative phase outputs 16B, 16A of the phase detector 14. As seen in this diagram, during normal operation (i.e., when the PLL is locked), the PLL clock signal 34 is in phase with the reference clock 12, but at a higher frequency. The PLL feedback signal 38 is nearly identical to the external reference clock signal 12 when the circuit is locked, and is in phase with this signal. When locking occurs, the phase difference between the PLL feedback signal 38 and the reference clock signal 12 is very small, and the phase detector 14 enters the "dead zone" region in which it cannot further discriminate between the phase difference of the two input signals 12, 38. In this region, the phase detector 14 outputs two extremely narrow pulses at the positive and negative phase outputs 16B, 16A, during the rising edge of the input clocks 12, 38.
One drawback of the circuit shown in FIG. 1 is the erratic performance of the system when the clock reference 12 becomes unavailable. For example, in fiber optic applications, a stable clock is required to generate an AIS signal when the system clock reference that locks every card becomes unavailable. When there is a reference failure, the PLL has to switch to a local crystal to be able to supply an AIS alarm signal to the far end equipment. Such a switch can cause a large frequency offset which is not desired in the optical environment. Prior attempts at solving this problem include forcing a fixed DC reference to the VCXO to establish a holdover value. This method is inaccurate and can cause the PLL output to largely exceed the SMC (SONET minimum clock)clock requirement.
Therefore, there remains a need in this field for an improved PLL circuit that overcomes the problems noted herein.